Real-time fourier transformation apparatus

ABSTRACT

An apparatus for performing real-time Fourier transformation of a time varying signal by taking successive digital samples in a shift register means and repeatedly transforming preselected pairs of said samples as the samples are progressively shifted down the register. The successive samples are ordered in the register in a binary sequence from 0 to 2n-1 while the pairs are selected when the binary distance between them is equal to 2n m, m being the transformation number, each pair xa,m, Xb,m being related to its transformed magnitude Xa,m 1 and Xb,m 1 by the relations

[ 1 Apr. 29, 1975 l l REAL-TIME FOURIER TRANSFORMATION APPARATUSInventors: George A. Works, Wayland; Harry Vickers. Oakham. both of Mass[73] Assignee: Raytheon Company, Lexington.

Mass.

[22] Filed: Oct. 30. 1973 [21] Appl.No.:4ll.l0l

Related U.S. Application Data OTHER PUBLlCATlONS G. Di Bergland & H. W.Hale, Digital Real-Time Spectral Analysis," IEEE Trans. on ElectronicComputers. Apr. 1967. pp, 180-185.

Primary Examiner-Charles E. Atkinson Amixmm hraminerDavid Hv MalzahnAttorney; Agent, or Firni.lohn R. lnge; Joseph D, Pannone; Milton DvBartlett l57| ABSTRACT An apparatus for performing real-time Fouriertransformation of a time varying signal by taking successive digitalsamples in a shift register means and repeatedly transformingpreselected pairs of said samples as the samples are progressivelyshifted down the register, The successive samples are ordered in theregister in a binary sequence from 0 to 2"l while the pairs are selectedwhen the binary distance between them is equal to 2" m being thetransformation number each pair x,, X,, being related to its transformedmagnitude X,, and X,, by the relations IIJII 'l mm lmu where d) is theradian value determined by the transform number in and the position ofthe sample pair X,, X,, in their original position order of successlont9 Claims. ll Drawing Figures 50 5? a l' ll F 5? 500 I 520 l I l i ll l78 5; l ize-n-mr n-BIT FREQUENCY TIME I FUNCTION FUNCT'ON REGlSTEFl IREGISTER l I 1 wono n r n z l l (CLOCK W72] 1 [54b 1 l l i ARITHMETIC Iumr l L we fl g -w CLOCK l 50 l PULS l 72 GENERATOR I 68 70 Ll- "a (READDNLY MEMORY TRlG. FUNCTlONSl ROTATION V ECTO R 58 STORAGE mgmmmzsms3.881 100 SHEET 10$ 6 DIAGRAM OF COOLEY TUKEY FFT ALGORITHM SWITCHCONTROL DATA SHIFT REGISTER DATA f f M #051 A= 2 SAMPLES r 5 AU F/GARITHMIXETIC Xum X x FFT MODULE b,m+| UNIT u,m+l 29 REAL |4u Ix n90 lSIYGD IMAGINARY s Q IMAGINARY IN /4 OUT HTENIEBIIPII29I9I5 3.881.100

saw 2 0F 6 ROTATION 80 ROTATION vEcTOR VECTOR ADDREss STORAGE 7 IIROTATION 50 52 54 s I I I DATA m= I m: DATA MODULE MODULE MODULE 62 5466 w T T I BINARY BINARY 76 60 COUNTER B'NARY COUNTER I won STAGECOUNTER STAGE CLOCK M36, STAGE SB) INPUT I i J x v I OUTPUT FREQUENCYCHANNEL AND ROTATION VECTOR NUMBER TO 82 ADDREss TO 80 FFT PROcEssOR 500520 540 78 DATA 56 SR SR I DATA INPUT m=I m=2 m=n OUTPUT /02\ 104 /06i\I08 //0 //2 1/4 H6 DATA BUs' ARITIINIETII:

UNIT

IOI

PATENTEDmzsma 3.881.100

SHEET 5 or 6 690 SHIFT PULSES MASTER TIMING CONTROLLER CTR 8 SYNCH AUSELECTOR SYNCH. COUNTER RO M S l NE COS ADDRESS TRANSLATO R ROM ROMSlNE/COSINE REVERSE LOGIC PATENTEDAPR29I915 SHEET B U? 6 FFT OUTPUTADDRESS UNIT SHIFT PULSES RTER ANALOG! DIGITAL F/G. 6B

REAL-TIME FOURIER TRANSFORMATION APPARATUS CROSS REFERENCE TO RELATEDAPPLICATIONS This is a division of application Ser. No. l ,948 filedNov. 24, I971 now US. Pat. No. 3,8l6,729, which is a streamlinedcontinuation of application Ser. No. 863,776 filed Oct. 6, I969, nowabandoned.

BACKGROUND OF THE INVENTION This invention relates to improvements inreal-time signal processing, and more particularly, to real-timedigitalized Fourier transformation of signals. The following paragraphsbriefly describe the relevant attempts to mechanize. using analog anddigital apparatus, the computation of these transforms. First, theFourier transform and signal processing is discussed to provide a basisfor appreciating the real-time requirements. Second, the discussioncenters on the problem of squaring real time requirements with the useof general purpose digital computers. Lastly, consideration is given tothe limitations of the current Fast Fourier Transform technique as usedon digital computers.

Fourier Transforms and Signal Processing The Fourier transform of asignal greatly enhances certain signal characteristics such as energy oramplitude distribution as a function of frequency. This helpsdiscriminate between a signal and noise. Typically, a transmissionenvironment includes broad-band noise. Such noise has a fairly uniformdistribution of energy over a large frequency range. In contrast, theFourier transformation of a signal will show a great deal of energyconcentrated in a comparatively narrow frequency band. The Fourierrelation is said to map a signal from the time domain into the frequencydomain. Mathematically, the relation between a signal as a function oftime .\'(I) and the transformation as a function of frequency X(w) is Inthis formulation, .\'(I) is an analytic continuous func tion. It,theoretically, requires integration of an infinite time interval and aknowledge of the future. However, the capacity of the transform to yieldfrequency spectrum information about a time varying signal greatlyoutweighs the failure of real world electrical signals to conform to theexactitude of mathematical analytic continuity. This is illustrated inthe following several examples.

A. B. Cunningham et al., US. Pat. No. 3,087,674 issued on Aprv 30, 1963,shows an analog Fourier transformation apparatus in which a time varyingelectrical signal .r(r) is partitioned to form sinusoidal componentproduct signals .rt!) sin w t and .r(1) cos w t. These product signalsare in turn integrated over time to yield I .t(1) sin w,-r dr and j.r(!) cos w tdr. Finally, the integrated product signals are combined toform an output signal X(w) such that By varying the given frequency ofthe range of interest m, W, s w, s W and recording the magnitude |X(w,-)l at each w,- there is obtained an analog record corresponding to aFourier transformation of the signal .\'(I).

Spectrum analyzers often include a bank of tuned narrow band widthcontiguous filters whose output yields a voltage versus frequencyspectrum. The square of the voltage versus frequency is proportional tothe power density spectrum of the corresponding signal. Also, a Dopplerradar range gate filter bank is one illustrative example of such aspectrum analyzer. In this regard, the filter bank may be thought of asa twodimensional spectrum of range versus Doppler frequency. Referencealso may be made to a voice communication example of M. R. Schroeder,U.Sv Pat. No. 3,344,349 issued on Sept. 26, 1967.

Real-Time Fourier Transform Processing A system reacts in real time whenthe complete response of a stimulated system occurs at, or about, thesame time as the stimulus. Generally, where a system needs the resultsof processing a time varying signal (stimulus) immediately, then a verybroadband width system is required. Such an overall signal processingrequirement exists for the Fourier transformation of radar echo returns.To impose the microsecond response time requirements of volume radardata upon prior art analog systems, in addition to a high degree ofaccuracy and precision, would clearly exceed all reasonable bounds ofcost, size, weight and power. Attention is directed to both Cunninghamet al. and Schroeder as illustrative of the high degree of complexity ofeven the low frequency band width analog processing arrangement.

Prior Art Digitalization of Fourier Transform Process If digitaltechniques are to be used for analyzing continuous waveforms, then it isnecessary that the data be sampled (usually at equally spaced intervalsoftime) in order to produce a time series of discrete samples which canbe fed into a digital computer. This time series can completelyrepresent the continuous waveform, if the waveform is frequencyband-limited and the samples are taken at a rate at least twice thehighest frequency present in the waveform.

A Discrete Fourier Transform (DFT) suitable for digital computationaluse is described in William T. Cochran et al., Proceedings of the IEEE,Volume 55, Number l0, October l967 at pages I665 to 1667. The DFT isdefined by the relation:

N1 XI: -215mm where X,- is the r component of the DFT; .r denotes the ksample of the time series consisting of N samples; r=0. l. 2. N l; andwhere j= l. Cochran further shows the substantial equivalence of DFT t0the continuous Fourier transform. lnspection of the above DFT relationreveals that each .o. must be multiplied N times to form N sums. Sincebe formed N times. Thus, every product term must be there are Ndifferent values ofx there must be comformed N times. The FFT algorithmbasically seeks to puted N multiplications and N additions. remove suchredundancy. For a derivation of the Coo- Programs for performing the DFTon general purley-Tukey version of FFT, reference is again made to posedigital computers have long been extant HOW- 5 Cochran et al,,especially between pages 1667 and ever, there are severe limitations tothe speed with 1669. which such machines can execute the programsvTypical processing times are in the order of 50 milliseconds. A varietyof notations have been used by different auln contrast, the channelcapacities (data volume) of thors in discussing the Fourier transform,DFT and such systems are not sufficient to accommodate reall0 FFT. Forconvenience all references in this disclosure time radar dataprocessing. lllustratively, a radar havhave been converted to a standardnotation; the following a one microsecond pulse width may require a dataing table compares Cochrans notation and the stanrate of million bitsper second, dard notation.

Quantity Standard Cochran Number of time or frequency samples in atransform block N N Base or radix of a transform R Number of stages in aradix R transform.

equal to log N n n K' time sample a :k Mali-. 1.

r'" frequency sample X l',. Z, 4,. 8,.

K'" output from m stage of FET Weighting term. or

rotation vectorv used in transform 1' t "-11' I It" The limitations of ageneral purpose device arise Briefly,Cochran et al.assumesatime scriesxhaving from the fact that such machines access main memories N samplesdivided into two functions y and z,,, each seriallyv Many of these haveword organized memories. comprising N/elements or points. y compriseseven Even the look ahead" machines, such as the IBM numbered points X Xx It comprises odd num- 7094 (STRETCH are limited to the extraction ofonly bered points .1 x .r Then,

a few words at a time from main core. Where data is y X packed andextracted on a word basis, there is difficulty x in accessing differentunits in different addresses. Thus, it W I. what emerges from the earlyattempted digital process- Let r and r represent the DFT yk and Zr.PfiC- ing was the need for a machine in which the data was iv lyuaccessible in parallel and byte organized.

1131 3 N The Fast Fourier Transform and Digitization -34m The FastFourier Transform (FFT) is an algorithm Z fs r:0 1 2 A g for computingthe Discrete Fourier Transform (DFT) r i 2 of a series of N (complexnumbers) data points in approximately N log N operations. As was pointedout by James W. Wooley et al., Proceedings of the IEEE, Vol Let W e 'rrthen X E .r W' 2 (y -l-zflw' ume 55, Number 10 at pages 1675 to I677,the FFT al- Now for O s r N/2 gorithm was devised specifically becausethe DFT re I 2 r (H217 r r r quiring N operations was using hundreds ofmachine hours of computing time". To appreciate FFT, it is nec- Forvalues of r N/2, the DFT Y, a d Z periodically essary to understand someofits derivation and relation repeat values taken when r N/2. Thus, -12lr+.\l2ll.\' j2 rIA' It should be recalled that in DFT NH YT+ 1r e y,w'z, km r Xr 1 1 l t21rr/\H f r 0 s r N/2. Then X, Fatc it where e 45cos d) +j sin d). According to Cochran, if the input digital data se-There are many repetitions in N computations of quence is stored incomputer memory in the order,

DFT. As an example. at k 0, the product 1 8 must for example, x .14.13;, I x x x then the computation may be done in placeY That is. theintermediate results will be written over" the original data sequence.Thus. no storage is needed beyond that required for the original Ncomplex numbers. However. what Cochran failed to appreciate was that ina general purpose digital computer having serially accessed stor age. R"data words must be transferred from the storage to the arithmetic unitin order to execute a fixed radix R transform upon N R" samples. Also.R" partial results must be transferred from the arithmetic unit back tostorage for each of n stages required to com pute the transform.Consequently. 2nR" accesses to storage are required.

Summary of the Invention It is. accordingly. an object of this inventionto devise an apparatus for computing Fourier transforms in real timeupon input time varying data. Itis a related object to devise a digitalresponsive apparatus having substantially simplified machineorganization.

The foregoing objects are attained in a preferred embodiment in whichsuccessive digital samples of a time varying signal taken at regularlyspaced intervals are inserted into shift register means. Preselectedpairs of said samples are repeatedly transformed as the sample pairs areprogressively shifted down the register. The successive samples areordered in the register in a binary sequence from 0 to 2"-l. The pairsare so chosen before each transformation such that the binary distancebetween them is equal to 2" m being the transformation number. Each pairX,, X is related to its transformed magnitude X,, and Xiunfl by therelations n.m+t mm lmn liJiHi uun Inm where d) is the radian valuedetermined by the transform number m and position of the sample pair intheir inverted position order of succession. In this regard. e" 4) isequivalent to Cochran's W. The successive signal samples aresequentially shifted such that each sample is selected and transformed ntimes.

It may be stated as a general proposition that N!/(NR)ER. differentcombinations of N samples taken R at a time may be extracted andtransformed in apparatus embodying the invention. Experience dictatesthat the invention is most efficient where R 2, 3. or 4.

There exist several embodiments of the machine. One embodiment uses anarithmetic unit common to all of the logic modules and time shared amongthem. Another embodiment uses a separate arithmetic unit for each logicmodule and is time shared only as between the Real and Imaginary datachannels of the logic module. In this latter embodiment. standardmodules are serially arranged. Time digital data samples reportingcomplex numbers are applied at the input of this cascade. Each logicmodule includes an arithmetic portion which operates upon the digitaldata sample transferred into the unit. This sample is then progressivelyshifted down the chain or cascade and transformed at each module.

The successive states or iteration of the fundamental (ooley-Tukeyalgorithm are each carried out in the separate cascaded modules In bothembodiments. shift registers are used as digital delay lines so as topermit new data to be entered into the processor while the processing ofearlier data can be carried out. Advantageously. the overall dclayrequired is only equal to the time necessary to gather the block of datain each of the Real and Imaginary channels. As the last or N" complexdata sample is loaded into this digital delay line, the first analysisappears at the output. The output frequencies appear in a sequenceassociated with the algorithm. A control device. namely. a binarycounter. yeilds digital numbers identifying both the channel number andthe frequency currently appearing at the output of the shift registerdigital delay line chain. Additionally. this binary counter specifiesthe instant at which the separate modules are to be switched and thedigital number identifying the sine/cosine values needed by each of themodules.

As mentioned in the Background. the requirement for real-time processingis most in demand with respect to radar information. In this context.data information is obtained at a high volume. In Doppler radar. it isoften desired to treat the phase shift information derived from thereceived echo signals as having a Real and Imaginary component. This isaccomplished by multiplying the detected Doppler signal by a sinusoidalfunction and processing it separately from the same signal multiplied bya sinusoidal function out of phase. Thus. the first stage of theserially connected logic modules may be made to terminate the radarreceiver in two parallel interconnected channels. one for processing theReal component of the radar data and the second channel for processingthe Imaginary component. Because the transform requires multiplying aportion of the data word in either channel by cd: an Imaginary componentwill be produced as a result of the multiplication. Accordingly.provision is further made for switching the Imaginary component producedby multiplication in the Real channel to the Imaginary channel of thenext successive module. Similarly. a Real component produced bymultiplication in the Imaginary channel is switchably connected to theReal channel at the next successive module.

It should be apparent that Imaginary components will be produced even ifonly Real components are present at the data input to the firstprocessing stage. Thus. it is necessary to retain this processingcapacity independent of the orthogonality requirements of the data asoriginally inputted to the FFT processor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a signal flow graph of aneight-point Cooley- Tukey Fast Fourier Transform algorithm.

FIGSv 2A and 28. respectively. show a block diagram and a detailed logicdiagram of a typical module used in the invention.

FIGS. 3A and 3B show the cascade of modules in relationship to thebinary counter stages and the rotation vector storage inputs.

FIG. 4 shows a block diagram of one embodiment of the invention in whichan arithmetic unit is time shared with all of the modules on a commonbus.

FIG. 5A is the signal flow diagram of a single module.

FIG. 5B is a detailed signal flow diagram of a 16- point transform asperformed by the invention. while FIG. 5C diagrammatically illustratesthe effect of the rotation vector 2 4,

FIGS. 6A and 6B are detailed logic block diagrams of the invention usingthe modules of FIGS. 2A and 2B and arranged generally as in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. I of thedrawings, there is shown a signal flow graph of the Cooley-Tukey algurithm. At the left of the graph are the data points .r through x; of thetime series 14,. which are to be trans formed by repeated applicationsofthe transform equations. Basically, this signal flow diagram iscomposed of nodes and arrows terminating in those nodes. The nodesrepresent the data or the data as transformed. The arrows originate atthe nodes whose variables contribute to the value of the variable at thenode at which the arrow terminates. The contributions at any node areadditive. The weight of each contribution, if other than unity, isindicated by the constant written close to the terminating arrow head.Thus, taking an arbitrary node and designating it u in FIG. I, it may beseen to be vectorally equal to x W.\',. Similarly, taking anotherarbitrary mode in FIG. I, I) would be equal to .r Wit As previouslymentioned, the computation may be done in place", that is, by writingall interme diate results over the original data sequence. Thus, forexample. the value of intermediate computations a and b are needed onlyfor two computations in the next successive transform T A iumllltlllud,each of the input nodes affects only t corresponding nodes immediatelyto the right. If the computation deals with two nodes taken at a time,the newly computed quantites may be ritten into the registers from whichthe input values 1 ere taken since the input values are no longer neededfor further computation (T,). The second step T also involves, forexample, pairs of nodes. After a new pair of results has been computed,the pair also may be stored in the registers which held the old resultsand are no longer needed.

A number ofimportant features of the algorithm may be seen by examiningthis figure. First, each stage follows a succeeding stage from left toright. Accordingly, each stage needs only the data generated from thepreceding stage. Second, if each stage processes information in theorder of arrival, then the first stage examines data points displaced byhalf the data length (N/2). The second stage examines data pointsseparated by one quarter the data length (NM). Third, if the data wereavailable in a continuous stream, then the first stage would process oneblock of data while the second stage processed the next earlier block ofdata and so on through all M stages. Fourth, the rotation vector 6 W hasthe same periodicity as the inverse of the data displacement interval,Finally, the data output is scrambled with respect to the order of thedata presented in the input.

Referring now to FIG. 2A, there is shown the basic module component ofthe invention. The m'" module alternately transfers blocks of 2""" datasamples at input I through switch 311 into the shift register SR on path1] and into the arithmetic unit AU on line 5. When the data block justfills the shift register SR, the arithmetic unit AU obtains at input 74a rotation vector from an external memory and begins its operation. Thenext block of 2""" data samples are sent to the arithmetic unit whichnow produces two complex number outputs X X in response to the twocomplex number inputs X,, and X,, One of the outputs X is immediatelytransferred over path 29 through switched connection 3b to a nextsuccessive stage while the other output X is returned to the input pathII of shift register SR through switched connection 3a. Thus. in theinterim period when shift register SR is being filled with new inputdata, then the former con tents of shift register SR containing theearlier transferred blocks are transferred to the next stage. With respect to all the data, the arithmetic unit AU computes the complexnumber twopoint transform X X X ,,,L and X,, I X,, X,, ,,,e where d) isthe radian value determined by the transform number m and the positionof the sample pair in their original position order of succession, a and17.

Referring now to FIG. 28, there is shown a more detailed implementationof the logic module set forth in FIG. 2A. It should be recalled that thetime varying analog signal values are converted to a binary digitalequivalent. It should further be recalled that many ap plications ofsampled data signals require processing of the original signal,sometimes called the Real signal, and the same signal shifted 90 out ofphase therewith. This is sometimes called an Imaginary signal. Each ofthe data points may be represented by a complex number. Accordingly, theReal and the Imaginary signals are represented collectively by complexnumbers. Furthermore, because the same two-point transform is applied toboth the Real and Imaginary signals, it is possible to share thearithmetic unit between them. This fact is amply illustrated in FIG. 2B.The Real signal is applied to input 4a, while the digits correspondingto the Imaginary input signal are applied to 4b. Arithmetic unit AU isshown in relationship to shift registers 16a and 16b and externallyprogrammed switches 12a,! um and ttimh- Referring now to the Real signalprocessing, the data input 4a is switchably connected through switch Sto either multiplier 32 or delay 14a. When S is coupled to multiplier32, the portion of the Real signal input constituting the Real componentof the complex number X,, is fed into the multiplier 32.

Switch S connects the shift register 16a to either the X output of adder38 through delay 400 or to the X,,,,,, input of the Real signal throughswitch S and delay 14a. Similarly, switch S couples register I60 to theoutput through delay I or applies the input X,, to adders 38 and 34. Itshould be noted that the lmaginary signal input applied at 412 isswitchably connected to multiplier 32 simultaneously with the realportion of the signal, and similarly to shift register 16!) throughdelay 14b and switch S Also, register 16b is selectively coupled toaccept the X output from adder 38 that is transmitted through delay 40band also through switch S Shift register 16b is selectively coupledthrough switch S to the Imaginary output through delay 18b, as well ascoupling the Imaginary signal X component into adders 38 and 34.

Switches 8, by selectively connecting delays 36a and 18a in the case ofswitch 8, and delays 36b and 18b in the case of switch S permit the Realand Imaginary two-point transforms to be read out simultaneously withthe application of a new complex input sample. Thus, X and Xconstituting the Real signal transform appear respectively throughdelays 36a and I80. Likewise, X and X constituting the Imaginary signaltransform appear respectively through delays 36b and 18b. The rotationvector is applied as an input to multiplier 32.

In order to analyze the gross operation of the module, let us recall theformulas The first step in solving the equations is to multiply e by X,,The X,, and X,, are obtained from a serial storage shift register whereReal and Imaginary components are stored in parallel. The e 11 term isof the form cos d) +j sin d). This is stored in rotation vector storagemeans 58. The correct e 1: term is sent to the arithmetic unit AU byexternal control logic. This will be discussed in greater detail withreference to FIGS 6A and 6B.

The complex multiplication is done in parts. This consists of four realmultiplications to form all the products of the two complex words andtwo real additions to form the final answer. The next step then is toadd and subtract this product from X,. to compute the final sum of thetransform. This requires four additions.

Referring now to FIG. 2B, the X,, input is applied in is complementformat and is converted into sign plus magnitude format. The multiplier32 works on numbers in sign plus magnitude format because of its economyand convenience. The multiplier 32 output is also converted into 1'scomplement format. Adders 34 and 38 utilize ls complement format inaddition. Also, the final output is further in ls complement format.

The detailed logic of multiplier 32 is not set forth explicity as thisis deemed to be well within the purview of one having ordinary skill inthe art. In this regard, reference may be made to any one ofa number ofstandard known works. such as Logic Design of Digital Computers" byMontgomery Phister, Jr., New York, John Wiley & Sons, 1959; A Survey ofSwitching Circuit Theory by McCluskey, Jr. and Bartee, McGraw- Hill BookCompany, Inc., New York, 1962', and Arithmetic Operations in DigitalComputers" by Richards, published by de Van Nostrand Company, Inc., NewYork, 1955. Suffice it to say that in the multiplier, provision must bemade for clocking the X terms in. The Real part may be stored in oneregister and the Imaginary part in another register, all withinmultiplier 32. In this regard, attention is directed to pages l36through l76 of Richards for several forms of multiplier logic.

The X terms should take only one word time in order to be clocked intothese multiplier registers. It is evident that the terms should beavailable from these registers in the form of the logical variable X andits logical complement form E The associated e do may be read in amultiplier buffer register also in parallel format. Preferably, itshould be read in at the same time that X,, is read in. Thus, both e itand X,, both their Real and imaginary parts, are available to beselected by the multiplier. In the design of such multiplier, it must beanticipated that several different clock times are necessary for formingdifferent products. Now, the multiplication of two complex numbersshould yield four partial products. of which two are Real and two areImaginary. A sign determination circuit can functionally comprise twocascaded half adders in sign magnitude multiplication. If eachmultiplier and the multiplicand form the same sign, then the partialproduct is positive. If the signs mismatch, then the partial product isnegative.

The output of multiplier 32 is X e This output is applied respectivelyas an input over two paths to ad ders 34 and 38. When either serialregister 16a or 16b is coupled to respectively paths constituting theX,, inputs for adders 34 and 38 through respective switch connections Sand S then X,, is also applied as an input to adders 34 and 38. Theoutput of adder 34 provides the sum X,, X,, ,,,e This sum is providedfor the Real signal through delay 36:: and the Imaginary signal throughdelay 36h. In a similar manner, the output of adder 38 is of the form XX,, ,,,e This dif ference for the Real signal appears through delay 40a.It is switchably connected to the Real output through switch S register16a, switch S and delay 18a. The difference relating to the Imaginaryoutput appears through delay 40b. It is switchably connected to theImaginary output through switch S register 16b, switch S and delay 18b.It is further apparent that the reading out of the two-point transformX,, X,, for the Real and Imaginary signals is achieved by alternatingrespective switches S between their re spective contacts.

Referring now to FIG. 3A, modules 50, 52, and 54 are serially arrangedwith data being applied at input 56 to the m=l module 50. Controlcounter 60, having counter stages 68, 70, and 72 corresponding to themodules. performs a timing or frequency division function as activatedby the word clock input 76. Each of the modules contains the logic shownin FIG. 2B. Paths 62, 64, and 66 couple corresponding counter stages 68,70, and 72 to modules 50, 52, and 54.

Rotation vector storage 58 supplies vector information 0 over a commonbus 74 to each of the modules. The rotation vector storage 58 maycomprise a read-only memory which is a table of sines and cosines sharedby all m modules. In FIG. 1, M2 different pairs of sines and cosines areread to process one block of N samples. It is important to note thatexactly M arithmetic units and exactly N complex number data points ofstorage are needed in the system. The first transform output from module54 appears at terminal 78 immediately after the last data sample in theblock of N data samples has been entered at the input 56.

The FFT processor shown in FIGS. 3A and 33 has a considerable speedadvantage. However, one-word delays must be inserted in or between theprocessing stages 50, 52, 54, etc., to make use of this speed. Thesedelays. discussed in reference to FIG. 2B, permit each module to begincomputation at the start of a word time rather than waiting for thepreceding modules to compute the input it requires.

These intermodule delays do not appreciably complicate the controlcircuitry of the FFT processor. It is only necessary to delay the datainput 56 and the rotation vector storage input 58 to each of the modules50, 52, and 54 by a number of word times equal to the total delay of thedata input. The control input to each module is a bit from the controlcounter 60. These bits may be transmitted to the modules over paths 62,64, and 66 from binary counter stages 68, 70, and 72, respectively. Thebits may be transmitted through actual delays (not shown). Delaycorrected control words for each module may be computed by subtractingthe appropriate delays from the control counter word.

Leaving the question of delays for a moment, each time a bit in thecontrol counter word changes from a zero to a one. the correspondingmodule controlled by that bit begins performing two-point transformsusing a new rotation vector ("4; Rotation vectors are therefore requiredat an average rate of one for each word time. These may be distributedto the processing modules on a single data bus 74. When intermodule andcontrol delays are considered, then the average rate at which rotationvectors are required is unchanged. However. buffer storage must beincluded between the data bus 74 and the modules for delay compensation.

Referring now to FIG. 313, there is shown a more de tailed block diagramof the embodiment illustrated in FIG. 3A. The time varying signalapplied at input 56 is in analog form and converted to digital form byanalogtodigital converter 57. A clock input signal is applied on bus 76for synchronizing converter 57, counter 60, and each of the shiftregister portions 50a, 52a, and 54a of the logic modules. As is apparentfrom the discussion of FIGS. 2A and 2B. the arithmetic units 50b, 52b,and 54b circulate a portion of their results into and out of thecorresponding shift register. The stages 68, 70, and 72 of counter 60perform a frequency division function. It should be noted that thedigital word from converter 57 is applied in parallel to the appropriategated shift register and gated in and out of the various registers inparallel. Of course, such an operation could also be done entirely inserial fashionv Rotation vector storage 58 comprises a storage medium inwhich a tabular form of sines and cosines may be stored in vectoraddresses corresponding to the posi tion indices and b of the extracteddata pair X,, and X,, in the serially arranged informationv The positionangle (1: 2111/2 where It is apparent that is determined by the length2""' of the shift register involved with each module since each moduleoperates on strings of data of given lengths. This fact may be observedby considering that m indicates the number of the arithmetic unit andthat 1' lies within the range 0 s i 2". The variable i is defined as thegreatest integer not greater than a/2- Il-Il|+l The structure of FIGS.3A and 38 may be readily modified to calculate inverse transforms whenthe spectral components are given in scrambled order. This structurepermits the same trade-off of channels pro cessed for data length perchannel by taking outputs at an intermediate stage.

Referring now to FIG. 4, there is shown an arithmetic unit 10] timeshared with shift registers 50a, 52a, and 540. on a common data bus 100.The output of shift register 500 results in N/2 independent two-pointtransforms. The output of shift register 52a yields N/4 independentfour-point transforms. Likewise. the output of shift register 54a yieldsN/S independent eightpoint transforms. If two independent streams ofcomplex number data were applied at data input 56 and interleaved onewith the other. then the m=first stage (500) would produce twoindependent discrete Fourier transforms of each data stream. Thespectral component of each channel of data is outputted before thespectral frequency is changed. What this means for pulsed radar or sonaris that where the data representing many range samples is received, thedata will be processed in order of arrival without modification andwithout requiring the data to be re-assembled into consecutive andnon-interleaved data streams.

The switches 102, 104, 106, I08, I10, 112, 114, and 116 are symbolicallyshown to indicate that the arithmetic unit 101 operating on a commondata bus may time share and process the output from any of the logicmodules 50a, 52a, and 54a.

Referring now to FIG. 58, there is shown a signal flow diagram of theCooley-Tukey algorithm for a 16- point transform. The input time samplesare in natural or monotonically progressive orderx x x r The transformresults in outputs X in bit reversed order X x X4 15 In order toimplement the transformation, it is necessary that successive modulesmust wait until the preceding module has completed its two-pointtransform and the X,, results have been passed on before the next modulecan begin transforming.

Alternatively. this signal flow diagram represents a series ofoperations to be performed on R-tuples of words of various distance inthe data string .r A data manipulating system which implements thisalgorithm must sequentially access all word Rtuples of distance R" R" 13R in the data string for a total of ZnR" accesses for a data string oflength R". The parameter R is the radix of the algorithm and n is anintegerv The value R is usually two or three. In FIG. 5B, R Z and thedata string is of length 2. Thus. for the first transformation timeinterval T the distance between pairs of digits which are to betransformed together is d R" 2*" 8, where m is the transformationnumber. Accordingly, the following digit pairs are se lected: x x .r,,.n, x 1, During the second trans formation time interval T the distancebetween pairs of digits taken from the transformation results of thefirst time interval T is d= 2"" 4. Then, the digits .t' occupying theformer cells may be combined as follows: .r' .r',,' .r' 1", Similarly.during the third transformation interval T the digits are selected witha distance of two units apart. Thus, the digits .t"

would be combined as follows: .r" x" x m lfi- As may be recalled, withrespect to the direction of the signal flow diagram in FIG. 1, the nodesat any point represent the summation of values terminating at the nodewith those nodes which have a weighting other than one. Thus, .t", .r',,W.r'

FIG. 5A is a simplified signal flow diagram illustrating the two-pointtransform. As can be seen, the complex number X,, ,,,e 41 isalgebraically added to X to form X,, As can be seen in this figure, therules for vector addition are the same as shown in FIGS. 1 and 5B.

Referring now to FIG. 5C, there is shown the rotational aspect of thevector e e 1 indicates a counterclockwise rotation of the vector,whereas e' i? is indicative of a clockwise rotation of the vector.

Referring to FIGS. 6A and 68, there is shown a detailed block diagram ofthe invention. A master or basic clock for the entire system iscontained within master timing control apparatus 600. The selected hardwire output lines 602, 604, 606 activate remote functional units of thesystem. Path 602 activates analog-to-digital converter 610. Inputcontrol path 604 activates register means 612 through 628 torespectively accept digital information from A/D converter 610. Outputcontrol path 606, also coupling register means 612 through 628, causesthe contents of register means 612 through 628 to be entered into Realregister 63! and Imaginary register 630. Shift pulse path 632 isterminated in Real and Imaginary registers 630 and 631. Pulses on thispath initiate the serial read-out of the contents of those registers.Paths 634, 636. 638, 640., 642, 644, 646, and 648 activate sample andhold circuits of the Real and Imaginary channel input means 650. Aspreviously discussed, these means essentially are used for radarapplications and other applications where it is desired to formquadrature or separate channel signals. Thus, sample data input signalsmultiplied by a sinusoid component are entered in Real register 652.Sample data signals multiplied by a sinusoid 90 out of phase with thefirst sinusoid are entered into Imaginary register 653. The contents ofthese registers are respectively serially read out on paths 656 and 655and are accordingly demultiplexed through switch means 658 as energizedover path 659 from the timing controller 600. The parallel entry of datainto selector switches 652 and 653 is controlled over paths 660, 661,and 662.

Logic modules 664 664,,,-: 664. are shown in cascade. Each of the shiftregisters SR is switchably connected in series with the shift registerSR of the next successive logic module. Data is entered into the logicmodule cascade on path 665 from Imaginary selector switch 630 and Realselector switch 631. The activation of the arithmetic unit ofapreselected logic module is controlled by AU selector 666 over paths667,,, 667 c 667,. The rotation e 4: vector is also gated into thecorresponding logic module from either read only memory 668 (for logicmodule 664 or readonly memory array 670 over path 672 (for logic modules664,,, 664,). The timing sequence for initiating the operation of thelogic modules is controlled by Master Timing Controller 600 throughMaster Synch Counter 674 over paths 667,,, 667 Similarly, the activationof the appropriate vector is derived from Master Timing Controller 600over path 675 to Synch Counter 676. Synch Counter 676 also regulates FFToutput and address unit 678 over path 679. It will be observed that FFToutput unit 678 is appropriately fed the Fourier transform data frommodule 664 over path 680.

The two point transformation data and the progressive shifting andtransforming of this data from the first logic module 664,,, through 664is described in detail with regard to FIGS. I through 5B. Broadly, theregularly spaced digitalized time data samples are entered on line 665into the first module and are progressively shifted under control of theMaster Timing Controller 600 and the appropriate Synchronizing andSelecting units 674, 666 to enable the presentation of the rotationvector from either memory unit 668 or memory arrangement 672 to bepresent at the appropriate logic module multiplier. The read-onlymemories (ROM) may be constructed from appropriate permanent memorymaterial or from any form of suitable bistable remanent magneticmaterial such as ferrite core arrays with an automatic rewriting of dataafter read. Synch Counter 676 also provides an input on path 672 overpath 682 in order to assure the proper gating in the rotation vectorinformation.

Memory arrangement 670 includes an address decoder 684, a translator685, driving each of three readonly memories 686, 687, and 688. Theaddress deoder is stimulated by the Synch Counter 676 upon signals onpath 675 from Timing Controller 600.

It is believed that the logical design of each of the requisitesubordinate units is well within the scope of the man ordinarily skilledin this art. For example, analog-to-digital converter 610 may range froma shaft po sition encoder to an appropriate diode resistance matrix. Thesample and hold circuits ofthe Real and Imaginary channel input means650 may be served by weighted capacitive means. These and otherarrangements described in detail. while suitable for one embodiment ofthis invention, are to be taken as suggestive and not as limiting. Aspreviously mentioned, a large variety of bistable remanent switchingdevices arranged in addressable register form may be devised to satisfythe requirements of this invention.

We claim:

I. A system for performing a Fourier transform com prising a pluralityof serially coupled computational stages, each stage comprising incombination:

means for performing arithmetic operations upon sets of data; means forstoring at least portions of said sets; means for coupling at leastportions of the results of said arithmetic operations upon said sets tosaid storing means; and said system further comprising single means forcontrolling each of said coupling means, said controlling meansoperating independently from any stored set of instructions.

2. The combination of claim I wherein said means for performingarithmetic operations comprises means for performing at least a portionof a discrete Fourier transform upon said sets.

3. The combination of claim 2 wherein said storing means comprises shiftregister storage means.

4. The combination of claim 2 wherein said storing means comprises anaddressable register.

5. The combination of claim 2 wherein said controlling means comprises acyclical binary counter.

6. In combination:

a single means for providing a cyclic count;

a plurality of memory means; and

arithmetic computation means coupled to each of said memory means forcalculating a discrete Fourier transformation upon a set of datasamples, said computation means including means for weighting at leastsome of said samples, said plurality of memory means and said arithmeticcomputation means all being synchronized by said single count providingmeans.

7. The combination of claim 6 wherein said means for providing a cycliccount comprises a cyclical binary counter.

8. The combination of claim 6 wherein said memory means comprises shiftregister means.

9. The combination of claim 7 wherein said memory means comprises anaddressable register.

1. A system for performing a Fourier transform comprising a plurality ofserially coupled computational stages, each stage comprising incombination: means for performing arithmetic operations upon sets ofdata; means for storing at least portions of said sets; means forcoupling at least portions of the results of said arithmetic operationsupon said sets to said storing means; and said system further comprisingsingle means for controlling each of said coupling means, saidcontrolling means operating independently from any stored set ofinstructions.
 2. The combination of claim 1 wherein said means forperforming arithmetic operations comprises means for performing at leasta portion of a discrete Fourier transform upon said sets.
 3. Thecombination of claim 2 wherein said storing means comprises shiftregister storage means.
 4. The combination of claim 2 wherein saidstoring means comprises an addressable register.
 5. The combination ofclaim 2 wherein said controlling means comprises a cyclical binarycounter.
 6. In combination: a single means for providing a cyclic count;a plurality of memory means; and arithmetic computation means coupled toeach of said memory means for calculating a discrete Fouriertransformation upon a set of data samples, said computation meansincluding means for weighting at least some of said samples, saidplurality of memory means and said arithmetic computation means allbeing synchronized by said single count providing means.
 7. Thecombination of claim 6 wherein said means for providing a cyclic countcomprises a cyclical binary counter.
 8. The combination of claim 6wherein said memory means comprises shift register means.
 9. Thecombination of claim 7 wherein said memory means comprises anaddressable register.